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3.1.9
Arming Threshold Registers (ARMT_XP, ARMT_XN, ARMT_YP, ARMT_YN)
These registers contain the X-axis and Y-axis positive and negative thresholds to be used by the arming function. Refer to
Section 3.8.9 for more details regarding the arming function.
These registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 3.1.6.2 . These
registers are included in the writable register CRC check. Refer to Section 3.2.2 for details.
Table 20. Arming Threshold Registers
Location
Bit
Address
$10
$11
$12
$13
Register
ARMT_XP
ARMT_YP
ARMT_XN
ARMT_YN
7
AT_XP[7]
AT_YP[7]
AT_XN[7]
AT_YN[7]
6
AT_XP[6]
AT_YP[6]
AT_XN[6]
AT_YN[6]
5
AT_XP[5]
AT_YP[5]
AT_XN[5]
AT_YN[5]
4
AT_XP[4]
AT_YP[4]
AT_XN[4]
AT_YN[4]
3
AT_XP[3]
AT_YP[3]
AT_XN[3]
AT_YN[3]
2
AT_XP[2]
AT_YP[2]
AT_XN[2]
AT_YN[2]
1
AT_XP[1]
AT_YP[1]
AT_XN[1]
AT_YN[1]
0
AT_XP[0]
AT_YP[0]
AT_XN[0]
AT_YN[0]
Reset Value
0
0
0
0
0
0
0
0
The values programmed into the threshold registers are the threshold values used for the arming function as described in
Section 3.8.9 . The threshold registers hold independent unsigned 8-bit values for each axis and polarity. Each threshold
increment is equivalent to one output LSB. Table 21 shows examples of some threshold register values and the corresponding
threshold.
Table 21. Threshold Register Value Examples
Axis Type
Programmed Thresholds
Range
(g)
20
20
50
120
Sensitivity
(g/LSB)
0.04097
0.04097
0.1024
0.24414
Positive
(Decimal)
100
255
50
20
Negative
(Decimal)
50
0
20
10
Positive Threshold
(g)
4.10
10.45
5.12
4.88
Negative Threshold
(g)
-2.05
Disabled
-2.05
-2.44
If either the positive or negative threshold for one axis is programmed to $00, comparisons are disabled for only that polarity.
The arming function still operates for the opposite polarity. If both the positive and negative arming thresholds for one axis are
programmed to $00, the Arming function for the associated axis is disabled, and the associated output pin is disabled, regardless
of the value of the A_CFG bits in the DEVCFG register.
3.1.10 Device Status Register (DEVSTAT)
The device status register is a read-only register. A read of this register clears the status flags affected by transient conditions.
Reference Section 4.5 for details on the MMA68xx response for each status condition.
Table 22. Device Status Register
Location
Bit
Address
$14
Register
DEVSTAT
7
UNUSED
6
IDE
5
SDOV
4
DEVINIT
3
MISOERR
2
OFF_Y
1
OFF_X
0
DEVRES
3.1.10.1
Unused Bit (UNUSED)
The unused bit has no impact on operation or performance. When read this bit may be ’1’ or ’0’.
3.1.10.2
Internal Data Error Flag (IDE)
The internal data error flag is set if a customer or OTP register data CRC fault or other internal fault is detected as defined in
Section 4.5.5 . The internal data error flag is cleared by a read of the DEVSTAT register. If the error is associated with a CRC fault
in the writable register array, the fault will be re-asserted and will require a device reset to clear. If the error is associated with the
data stored in the fuse array, the fault will be re-asserted even after a device reset.
MMA68xx
Sensors
Freescale Semiconductor, Inc.
19
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